Navigation

  • index
  • next |
  • previous |
  • envytools git documentation »
  • nVidia hardware documentation »

Video decoding, encoding, and processing¶

Contents:

  • VPE video decoding and encoding
    • PVPE: video decoding/encoding engine control
    • PMPEG: MPEG1/MPEG2 video decoding engine
    • PME: motion estimation
      • Overview of VPE motion estimator
    • PVP1: video processor
      • Overview of VP1 video processor
      • Scalar unit
      • Vector unit
      • Branch unit
      • Address unit
      • DMA transfers
      • FIFO interface
  • VP2/VP3 vµc processor
    • Overview of VP2/VP3/VP4 vµc hardware
    • VP2/VP3/VP4 vµc ISA
    • VP2/VP3/VP4 vµc MVSURF
    • VP2/VP3/VP4 vµc video registers
    • VP2 vµc output
    • vµc performance monitoring signals
  • VP2 video decoding
    • VP2 xtensa processors
    • PVP2: video processor
    • PBSP: H.264 bitstream processor
    • VLD: variable length decoding
    • MBRING format
    • VP2 command macro processor
    • PCIPHER: AES encryption engine
  • VP3/VP4/VP5 video decoding
    • PVLD: variable length decoding engine
    • PPDEC: picture decoding engine
    • PPPP: video post-processing engine
    • PSEC: AES cryptographic security engine
    • VP3 MBRING format
    • PVDEC: video decoding engine
  • PVCOMP: video compositor engine
  • PVENC: video encoding engine
  • PVDEC: VP6 video decoding engine

Previous topic

Cryptographic coprocessor

Next topic

VPE video decoding and encoding

This Page

  • Show Source

Quick search

Navigation

  • index
  • next |
  • previous |
  • envytools git documentation »
  • nVidia hardware documentation »
© Copyright 2013, Marcelina Kościelnicka. Created using Sphinx 1.8.6.