Second-level interrupts

Because falcon has space for only 8 engine interrupts and PDAEMON needs many more, a second-level interrupt register was introduced:

MMIO 0x688 / I[0x1a200]: SUBINTR


figure out bits 7, 8


more bits in 10-12?

The second-level interrupts are merged into a single level-triggered interrupt and delivered to falcon interrupt line 11. This line is asserted whenever any bit of SUBINTR register is non-0. A given SUBINTR bit is set to 1 whenever the input second-level interrupt line is 1, but will not auto-clear when the input line goes back to 0 - only writing 1 to that bit in SUBINTR will clear it. This effectively means that SUBINTR bits have to be cleared after the downstream interrupt. Note that SUBINTR has no corresponding enable bit - if an interrupt needs to be disabled, software should use the enable registers corresponding to individual second-level interrupts instead.

Note that IREDIR_HOST_REQ interrupt has special semantics when cleared - see IREDIR_TRIGGER documentation.