PCRTC: scanout engine


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MMIO registers


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8-bit space pcrtc [0x1000]
nv3-mmio 0x600000: PCRTC [NV4:NV11,NV20:NV25]
nv3-mmio 0x600000+i*0x2000: PCRTC[i] (i<2) [NV11:NV20,NV25:G80]


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8-bit space prmcio [0x1000]
nv3-mmio 0x601000: PRMCIO [NV3:NV11,NV20:NV25]
nv3-mmio 0x601000+i*0x2000: PRMCIO[i] (i<2) [NV11:NV20,NV25:G80]


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Address Name Description
0x3d0 RMA_ACCESS RMA access port
0x3d4 CRTC_INDEX CRTC index
0x3d5 CRTC_DATA CRTC data



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RMA access port

reg32 nv3-io-rma-access
prmcio 0x3d0: RMA_ACCESS

This is a 32-bit port that writes into the RMA address specified by CRTC register 0x38.

CRTC registers

reg8 nv3-io-crtc-index
prmcio 0x3d4: CRTC_INDEX
reg8 nv3-io-crtc-data
prmcio 0x3d5: CRTC_DATA
8-bit space nv3-crtc-ext-regs [0x100]
Address Name Description
0x19 REPAINT_0 Extended Start Address and Row Offset
0x1a REPAINT_1 Repaint 1
0x1d WRITE_BANK Write bank
0x1e READ_BANK Read bank
0x25 EXTENDED_VERT Extended Vertical Bits
0x28 PIXEL_FMT Pixel Format
0x2d EXTENDED_HORZ Extended Horizontal Bits
0x38 RMA_MODE RMA mode register
0x3e I2C_READ I2C read register
0x3f I2C_WRITE I2C write register
reg8 nv3-crtc-ext-rpc0
nv3-crtc-ext-regs 0x19: REPAINT_0

Bits 4-0 are Start Address bits 16-20. Bits 7-5 are Row Offset bits 3-5.

reg8 nv3-crtc-ext-rpc1
nv3-crtc-ext-regs 0x1a: REPAINT_1

Bit 2 shifts the row offset either left or right by 1 bit, I forget which way.

reg8 nv3-crtc-ext-write-bank
nv3-crtc-ext-regs 0x1d: WRITE_BANK

Write bank for real mode access of the VGA framebuffer in 32k units.

reg8 nv3-crtc-ext-read-bank
nv3-crtc-ext-regs 0x1e: READ_BANK

Read bank for real mode access of the VGA framebuffer in 32k units.

reg8 nv3-crtc-ext-extvert
nv3-crtc-ext-regs 0x25: EXTENDED_VERT

Bit 0 is Vertical Total bit 10. Bit 1 is Vertical Display End bit 10. Bit 2 is Vertical Blank Start bit 10. Bit 3 is Vertical Sync Start bit 10. Bit 4 is Horizontal Total bit 8.

reg8 nv3-crtc-ext-pixel-fmt
nv3-crtc-ext-regs 0x28: PIXEL_FMT

Bits 1-0 are Pixel Format. 0 is VGA, 1 is 8bpp, 2 is 16bpp, and 3 is 32bpp.

reg8 nv3-crtc-ext-exthorz
nv3-crtc-ext-regs 0x2d: EXTENDED_HORZ

Bit 0 is Horizontal Display End bit 8.

reg8 nv3-crtc-ext-rmamode
nv3-crtc-ext-regs 0x38: RMA_MODE

Bit 0 enables port 0x3d0 when high, bits 3-1 are which RMA register to write to.

reg8 nv3-crtc-ext-i2c-read
nv3-crtc-ext-regs 0x3e: I2C_READ

Bit 3 is SDA, Bit 2 is SCL.

reg8 nv3-crtc-ext-i2c-write
nv3-crtc-ext-regs 0x3f: I2C_WRITE

Bit 5 is SCL, Bit 4 is SDA.