PFB: NV1 native display and VRAM controller engine

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Introduction

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The MMIO registers

8-bit space nv1-pfb [0x1000]
nv1-mmio 0x600000: PFB
Address Name Description
0x0 VRAM_CONFIG VRAM configuration
0x40 UNK040 VRAM ???
0x44 UNK040 VRAM ???
0x80 UNK080 VRAM ???
0xc0 POWER_SYNC Power state and sync pulse config
0x200 CONFIG Display and framebuffer configuration
0x400 START Display start address
0x500 HOR_FRONT_PORCH Horizontal front porch size
0x510 HOR_SYNC_WIDTH Horizontal sync pulse size
0x520 HOR_BACK_PORCH Horizontal back porch size
0x530 HOR_DISP_WIDTH Horizontal display size
0x540 VER_FRONT_PORCH Vertical front porch size
0x550 VER_SYNC_WIDTH Vertical sync pulse size
0x560 VER_BACK_PORCH Vertical back porch size
0x570 VER_DISP_WIDTH Vertical display size

VRAM control

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reg32 nv1-pfb-vram-config
nv1-pfb 0x0: VRAM_CONFIG
  • bits 0-1: VRAM_SIZE

    VRAM size, one of:

    • 0: 1MB
    • 1: 2MB
    • 2: 4MB
  • bits 8-9: ???

  • bit 12: ???

  • bits 16-17: ???

  • bit 20: ???

  • bit 24: ???

  • bit 28: ???

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reg32 nv1-pfb-unk040
nv1-pfb 0x40: UNK040

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reg32 nv1-pfb-unk044
nv1-pfb 0x44: UNK040

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reg32 nv1-pfb-unk080
nv1-pfb 0x80: UNK080

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Framebuffer configuration

One of PFB’s tasks is managing the framebuffer that PGRAPH will draw to. This (and a few assorted functions) is handled by the following register:

reg32 nv1-pfb-config
nv1-pfb 0x200: CONFIG
  • bit 0: VBLANK - read only, 1 iff the scanout hardware is currently in vblank.

  • bits 4-6: CANVAS_WIDTH - determines the width of canvas used by PGRAPH, in pixels. One of:

    • 0: 576 pixels,
    • 1: 640 pixels,
    • 2: 800 pixels,
    • 3: 1024 pixels,
    • 4: 1152 pixels,
    • 5: 1280 pixels,
    • 6: 1600 pixels,
    • 7: 1856 pixels,

    This only affects PGRAPH, and not scanout. However, PGRAPH is quite useless, unless this is set to be the same as the screen width used by scanout.

  • bits 8-9: BPP - determines the size of a pixel. This affects both PGRAPH and scanout. The DAC has a similiar setting in one of its registers, and they should be set identically, or display data will be mangled. One of:

    • 0: 4bpp (not supported by PGRAPH, which will behave as if it was set to 8bpp),
    • 1: 8bpp,
    • 2: 16bpp,
    • 3: 32bpp.
  • bit 12: DOUBLE_BUFFER - if set, VRAM is split in two halves, which PGRAPH will treat as two separate framebuffers. Also, RAMIN will be interleaved across the halves. If not set, there is only one buffer. This setting does not affect scanout.

  • bits 16-18: ???

  • bit 20: SCANLINE - ???

  • bits 24-26: PCLK_VCLK_RATIO - ???

  • bit 28: ???

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unknowns

See The PGRAPH framebuffer for details on framebuffer layout.

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Scanout hardware

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reg32 nv1-pfb-power-sync
nv1-pfb 0xc0: POWER_SYNC

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reg32 nv1-pfb-start
nv1-pfb 0x400: START

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reg32 nv1-pfb-hor-front-porch
nv1-pfb 0x500: HOR_FRONT_PORCH

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reg32 nv1-pfb-hor-sync-width
nv1-pfb 0x510: HOR_SYNC_WIDTH

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reg32 nv1-pfb-hor-back-porch
nv1-pfb 0x520: HOR_BACK_PORCH

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reg32 nv1-pfb-hor-disp-width
nv1-pfb 0x530: HOR_DISP_WIDTH

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reg32 nv1-pfb-ver-front-porch
nv1-pfb 0x540: VER_FRONT_PORCH

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reg32 nv1-pfb-ver-sync-width
nv1-pfb 0x550: VER_SYNC_WIDTH

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reg32 nv1-pfb-ver-back-porch
nv1-pfb 0x560: VER_BACK_PORCH

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reg32 nv1-pfb-ver-disp-width
nv1-pfb 0x570: VER_DISP_WIDTH

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